1. Field of the Invention
This invention relates generally to improved integrated semiconductor structures including fabrication methods therefor, and, more particularly, to improved integrated semiconductor transistor structures having dielectric sidewall isolation and PN junction substrate isolation including fabrication methods therefor.
2. Background of the Prior Art
Related References ______________________________________ U.S. Pat. No. 3,617,822 3,648,128 3,617,826 3,659,160 3,736,193 ______________________________________
In the past, integrated semiconductor structures were fabricated using PN junction isolation in order to electrically isolate various transistor or other devices (diodes, resistors, etc.) from each other. The PN junction isolated devices usually had a substrate of one type conductivity and the collector of the transistor device, for example, having a region of opposite type conductivity was located on the substrate and biased with respect to the substrate in a manner to utilize the PN junction between the substrate and the collector of the device for the purpose of electrically isolating the device from the substrate.
Other techniques were developed for isolating devices in an integrated semiconductor structure. One of these techniques included the concept of dielectric isolation. In this technique of isolation, the various semiconductor devices were formed in pockets of monocrystalline semiconductor material which pockets were isolated from an underlying substrate by means of a dielectric layer of material, usually of silicon dioxide. The dielectric isolated semiconductor devices had a very big advantage over PN junction isolated devices in that there was no need to use reverse biased techniques to set up the PN junction isolation and also there was no fear of the possible breakdown of the PN junction.
Subsequently, PN junction isolated structures were developed using dielectric isolated sidewall regions in combination to provide integrated semiconductor structures using the methods of both isolation techniques. One primary advantage attributed to the PN junction isolated structure over the dielectric isolated substrate concept is that the PN junction substrate isolated device can be generally made more simpler (less fabrication steps) and more planar than the more complex dielectric substrate isolated type of structure.
One recently developed technique used in the combination of PN junction and dielectric isolated structures produced the "VIP" semiconductor integrated structure wherein a V-shaped moat which was formed around the individual transistor devices was subsequently filled by means of a V-shaped silicon dioxide isolation layer followed by a filled in polycrystalline semiconductor material which thereby formed the "VIP" isolation channel. The V stands for the shape of the moat, the I stands for isolation formed by the dielectric material, and the P stands for the polycrystalline silicon used to fill in the moat and thereby make the structure substantially planar.
A need existed to develop an improved version of the "VIP" integrated semiconductor structure which would have the following features:
1. A good low resistance contact to the buried sub-collector region of the transistor device. PA1 2. Very small device geometries thereby conserving important silicon real estate on the chip. PA1 3. Only dielectric sidewall isolation and PN junction isolation between the substrate and the device.